| 1. | Instruction to force the cache line containing the modified instruction to storage
指令，强制包含有修改过的指令的高速缓存行进行存储。 |
| 2. | Instruction to invalidate the instruction cache line that will contain the modified instruction
指令，使将要存放修改后指令的指令高速缓存行无效。 |
| 3. | Cache memory is constructed with high - speed static random access memory ( sram ) , managed in a unit called cache line
当cache中保存着cpu要读写的数据时， cpu直接访问cache 。 |
| 4. | This kind of performance can match the speed of microprocessor bus operation . the size of a cache line is usually a few processor words
由于cache的速度与cpu相当， cpu能在零等待状态下迅速地实现数据存取。 |
| 5. | Instruction to clear the instruction pipeline of any instruction that may have already been fetched from the cache line prior to the cache line being invalidated
指令，清除所有指令的指令管道，那些指令在高速缓存行被设为无效之前可能早已被取走了。 |
| 6. | At the same time , we propose an optimization methodology for power minimization by reconfiguring the organization of cache and changing the form of words stored in some cache lines
在设计上突破传统思想的约束，采用可重构技术降低cache的功耗。所谓可重构技术是指系统中的硬件结构可以根据应用程序的需求进行重新配置。 |
